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preliminary cybl10x6x family datasheet programmable radio-on-chip with bluetooth low energy (proc ble) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-90478 rev. *f revised november 11, 2014 general description proc ble is a 32-bit, 48-mhz arm ? cortex?-m0 ble solution with capsense ? , 12-bit adc, four timer, counter, pulse-width modulators (tcpwm), thirty-six gpios, two se rial communication blo cks (scbs), lcd, and i 2 s. proc ble includes a royalty-free ble stack compatible with bluetooth ? 4.1 and provides a complete, programmable, an d flexible solution for hid, remote controls, toys, beacons, and wireless chargers. in addition to these applic ations, proc ble provides a simple, low-cost way to add ble connectivity to any system. features bluetooth ? smart connectivity bluetooth 4.1 single-mode device 2.4-ghz ble radio and baseband with integrated balun tx output power: ?18 dbm to +3 dbm received signal strength indicator (rssi) with 1-db resolution rx sensitivity: ?92 dbm tx current: 15.6 ma at 0 dbm rx current: 16.4 ma arm cortex-m0 cpu core 32-bit processor (0.9 dmips/mh z) with single-cycle 32-bit multiply, operating at up to 48 mhz 128-kb flash memory 16-kb sram memory emulated eeprom using flash memory watchdog timer with dedicated internal low-speed oscillator (ilo) ultra-low-power 1.3-a deep-sleep mode with watch crystal oscillator (wco) on 150-na hibernate mode current with sram retention 60-na stop mode curr ent with gpio wakeup capsense ? touch sensing with two-finger gestures up to 36 capacitive sensors for buttons, sliders, and touchpads two-finger gestures: scroll, iner tial scroll, pinch, stretch, and edge-swipe cypress capacitive sigma-delta (csd) provides best-in-class snr (> 5:1) and liquid tolerance automatic hardware-tuning algorithm (smartsense?) peripherals 12-bit, 1-msps sar adc wi th internal reference, sample-and-hold (s/h), and channel sequencer ultra-low-power lcd segment drive for 128 segments with operation in deep-sleep mode two serial communication blocks (scbs) supporting i 2 c (master/slave), spi (master/slave), or uart four dedicated 16-bit tcpwms ? additional four 8-bit or two 16-bit pwms programmable lvd from 1.8 v to 4.5 v i 2 s master interface clock, reset, and supply wide supply-voltage range: 1.9 v to 5.5 v 3-mhz to 48-mhz internal main oscillator (imo) with 2% accuracy 24-mhz external clock oscillator (eco) without load capaci- tance 32-khz wco programmable gpios 36 gpios configurable as open drain high/low, pull-up/pull-down, hi-z , or strong output any gpio pin can be capsense, lcd, or analog, with flexible pin routing programming and debug 2-pin swd in-system flash pr ogramming support temperature and packaging operating temperature range: ?40 c to +85 c available in 56-pin qfn (7 mm 7 mm) and 68-ball wlcsp (3.52 mm 3.91 mm) packages psoc ? creator? design environment easy-to-use ide to configure, develop, program, and test a ble application option to export the design to keil, iar, or eclipse bluetooth low energy protocol stack bluetooth low energy protocol stack supporting generic access profile (gap) central, peripheral, observer, or broad- caster roles ? switches between central and peripheral roles on-the-go standard bluetooth low energy profiles and services for interoperability ? custom profile and service for specific use cases errata: for information on silicon errata, see ?errata? on page 40. details include trigger conditions, devices affected, and proposed workaround.
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 2 of 42 contents blocks and functionality ............. .............. .............. ........ 3 cpu subsystem .......................................................... 4 ble subsystem........................................................... 4 system resources subsystem .. .............. .............. ..... 4 peripheral blocks ...... .............. .............. .............. ........ 5 pinouts .............................................................................. 8 power............................................................................... 13 low-power modes ..................................................... 13 development support .................................................... 15 documentation .......................................................... 15 online ........................................................................ 15 tools.......................................................................... 15 kits ............................................................................ 15 electrical specifications ................................................ 16 absolute maximum ratings..... .................................. 16 ble subsystem......................................................... 16 device-level specifications ...................................... 19 analog peripherals .... .............. .............. .............. ...... 24 digital peripherals ..................................................... 26 memory ..................................................................... 29 system resources .................................................... 29 ordering information...................................................... 33 part numbering conventions ... ................................. 33 packaging........................................................................ 35 acronyms ........................................................................ 37 document conventions ................................................. 39 units of measure ....................................................... 39 errata ............................................................................... 40 errata summary ........................................................ 40 revision history ............................................................. 41 sales, solutions, and legal information ...................... 42 worldwide sales and design supp ort............. .......... 42 products .................................................................... 42 psoc? solutions ...................................................... 42 cypress developer community................................. 42 technical support .................. ................................... 42
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 3 of 42 blocks and functionality the cybl10x6x block diagram is shown in figure 1 . there are five major subsystems: cpu subsystem, ble subsystem, system resources, peripheral blocks, and i/o subsystem. figure 1. block diagram the proc ble family includes extensive support for programming, testing, debugging, and tracing both hardware and firmware. the complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator ide provides fully integrated programming and debug support for proc ble devices. the swd interface is fully compatible with industry-standard third-party tools. proc ble also supports disabling the swd interface and has a robust flash-protection feature.
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 4 of 42 cpu subsystem cpu the cybl10x6x device is based on an energy-efficient arm cortex-m0 32-bit processor, offering low power consumption, high performance, and reduced code size using 16-bit thumb instructions. the cortex-m0?s ability to perform single-cycle 32-bit arithmetic a nd logic operatio ns, including single-cycle 32-bit multiplicati on, helps in better performance. the inclusion of the tightly-integrated nested vectored interrupt controller (nvic) with 32 interrupt lines enables the cortex-m0 to achieve a low latency and a deterministic interrupt response. the cpu also includes a 2-pin interface, the serial wire debug (swd), which is a 2-wire form of jtag. the debug circuits are enabled by default and can only be disabled in firmware. if disabled, the only way to re-enable them is to erase the entire device, clear flash protection, a nd reprogram the device with the new firmware that enables debugging. in addition, it is possible to use the debug pins as gpio t oo. the device has four break- points and two watchpoints for effective debugging. flash the device has a 128-kb flash memory with a flash accelerator, tightly coupled to the cpu to im prove average access times from flash. the flash is designed to deliver 1-wait-state (ws) access time at 48 mhz and with 0-ws access time at 24 mhz. the flash accelerator delivers 85% of si ngle-cycle sram access perfor- mance on average. part of the flash can be used to emulate eeprom operation, if required. during flash erase and programming operations (the maximum erase and program time is 20 ms per row), the imo will be set to 48 mhz for the duration of the operation. this also applies to the emulated eeprom. system design mu st take this into account because peripherals operating from different imo frequencies will be affected. if it is critical that peripherals continue to operate with no change during flash programming, always set the imo to 48 mhz and derive the peripheral clocks by dividing down from this frequency. sram the low-power 16-kb sram memory retains its contents even in hibernate mode. rom the 8-kb supervisory rom contains a library of executable functions for flash programming. these functions are accessed through supervisory calls (svc) and enable in-system programming of the flash memory. ble subsystem the ble subsystem consists of the link layer engine and physical layer. the link layer engine supports both master and slave roles. the link layer engine implements time-critical functions such as encryption in the hardware to reduce the power consumption, and provides minimal processor inter- vention and a high performance. the key protocol elements, such as host control interface (h ci) and link control, are imple- mented in firmware. the direct test mode (dtm) is included to test the radio performance using a standard bluetooth tester. the physical layer consists of a modem and an rf transceiver that transmits and receives ble packets at the rate of 1 mbps over the 2.4-ghz ism band. in the transmit direction, this block performs gfsk modulation and then converts the digital baseband signal of these ble packets into radio frequency before transmitting them to air through an antenna. in the receive direction, this block converts an rf signal from the antenna to a digital bit stream after performing gfsk demodulation. the rf transceiver contains an integrated balun, which provides a single-ended rf port pin to drive a 50- ? antenna terminal through a pi-matching network. the output power is program- mable from ?18 dbm to +3 dbm to optimize the current consumption for different applications. the bluetooth low energy protocol stack uses the ble subsystem and provides the following features: link layer (ll) ? master and slave roles ? 128-bit aes engine ? encryption ? low-duty-cycle advertising (bluetooth 4.1 feature) ? le ping (bluet ooth 4.1 feature) bluetooth low energy 4.1 single-mode protocol stack with logical link control and adaptati on protocol (l2cap), attribute (att), and security manager (sm) protocols master and slave roles api access to generic attribute profile (gatt), generic access profile (gap), and l2cap l2cap connection-oriented ch annel (bluetoot h 4.1 feature) gap features ? broadcaster, observer, peripheral, and central roles ? security mode 1: level 1, 2, and 3 ? security mode 2: level 1 and 2 ? user-defined advertising data ? multiple-bond support gatt features ? gatt client and server ? supports gatt subprocedures ? 32-bit universally unique identifiers (uuid) (bluetooth 4.1 feature) security manager (sm) ? pairing methods: just wor ks, passkey entry, and out of band ? authenticated man-in-the-middle (mitm) protection and data signing supports all sig-adopted ble profiles system resources subsystem power the power block includes internal ldos that supply required voltage levels for different blocks. the power system also includes por, bod, and lvd circuits. the por circuit holds the device in the reset state until the power supplies have stabilized at appropriate levels and the clock is ready. the bod circuit resets the device when the supply voltage is too low for proper device operation. the lvd circuit generates an interrupt if the supply voltage drops below a user-selectable level.
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 5 of 42 an external active-low reset pin (xres) can be used to reset the device. the xres pin has an internal pull-up resistor and, in most applications, does not require any additional pull-up resistors. the power system is described in detail in the ?power? section on page 13. clock control the proc ble clock control is responsible for providing clocks to all subsystems and also for s witching between different clock sources without glit ching. the clock control for proc ble consists of the imo and the intern al low-speed oscillator (ilo). it uses the 24-mhz external crystal oscillator (eco) and the 32-khz wco. in addition, an external clock may be supplied from a pin. the device has 12 dividers with 16 divider outputs. two dividers have additional fractional division capability. the hfclk signal is divided down, as shown in figure 2 , to generate the system clock (sysclk) and peripheral clock (perx_clk) for different peripherals. the system clock (sysclk) driving buses, registers, and the processor mu st be higher than all the other clocks in the system that are divided off hfclk. the eco and wco are present in the ble s ubsystem and the clock outputs are routed to the system resources. internal main oscillator (imo) the imo is the primary system clock source, which can be adjusted in the range of 3 mhz to 48 mhz in steps of 1 mhz. the imo accuracy is 2%. internal low-speed oscillator (ilo) the ilo is a very-low-power 32-kh z oscillator, which is primarily used to generate clocks for peripheral operations in deep-sleep mode. the ilo-driven counters can be calibrated to the imo to improve accuracy. cypress provides a software component, which does the calibration. figure 2. clock control external crystal oscillator (eco) the eco is used as the active clock for the ble subsystem to meet the 50-ppm clock accuracy requirement of the bluetooth 4.1 specification. the eco includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. the high-accuracy eco clock can also be used as a system clock. watch crystal oscillator (wco) the wco is used as the sleep clock for the ble subsystem to meet the 500-ppm clock accuracy requirement of the bluetooth 4.1 specification. the sleep clock provides accurate sleep timing and enables wakeup at specified advertisement and connection intervals. with the wco and firmware, an accurate real-time clock (within the bounds of the 32.768-khz crystal accuracy) can be realized. voltage reference the internal bandgap reference circuit with 1% accuracy provides the voltage reference for the 12-bit sar adc. to enable better snrs and absolute accuracy, it will be possible to bypass the internal bandgap reference using a ref pin and to use an external reference for the sar. watchdog timer (wdt) a watchdog timer is implemented in the system resources subsystem running from the ilo; this allows watchdog opera- tions during deep-sleep mode and generates a watchdog reset if not serviced before the tim eout occurs. the watchdog reset is recorded in the ?reset cause? register. peripheral blocks 12-bit sar adc the adc is a 12-bit, 1-msps sar adc with a built-in sample-and-hold (s/h) circuit. the adc can operate with either an internal voltage reference or an external voltage reference. preceding the sar adc is the sarmux, which can route external pins and internal signals (analog mux bus and temper- ature sensor output) to the eight internal channels of the sar adc. the sequencer controller (sarseq) is used to control the sarmux and sar adc to do an automatic scan on all enabled channels without cpu intervention and for preprocessing tasks such as averaging the output data. a cypress-supplied software driver (component) is used to control the adc peripheral. figure 3. sar adc system diagram imo ilo extclk lfclk prescaler sysclk divider 0 (/16) per0_clk divider 9 (/16) fractional divider 0 (/16.5) eco wco hfclk per15_clk divider /2 n (n=0..3) fractional divider 1 (/16.5) ? ble subsystem ahb, dsi saradc vplus vminus sequencer configure r egisters sarseq sarref p3.0 ? p3.7 vrefs ref-bypass analog mux bus a/b data control sarmux
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 6 of 42 a diode based, on-chip temperature sensor is used to measure the die temperature. th e temperature sensor is connected to the adc, which digitizes the reading and produces a temperature value using the cypress-supplied software that includes calibration and linearization. 4x timer counter pwm (tcpwm) the 16-bit tcpwm module can be used to generate the pwm output or to capture the timing of edges of input signals or to provide a timer functionality. tcpwm can also be used as a 16-bit counter that supports up, down, and up/down counting modes. rising edge, falling edge, combined rising/falling edge detection, or pass-through on all hardware input signals can be used to derive counter events. three r outed output signals are available to indicate underflow, overflow, and counter/compare match events. a maximum of four tcpwms are available. 4x pwm these pwms are in addition to the tcpwms. the pwm peripheral can be configured as 8-bit or 16-bit resolution. the pwm provides compare outputs to generate single or continuous timing and control signals in hardware. it also provides an easy method of generating complex real-time events accurately with minimal cpu interventi on. a maximum of four 8-bit pwms or two 16-bit pwms are available. serial communication block (scb0/scb1) the scb can be configured as an i 2 c, uart, or spi interface. it supports an 8-byte fifo for receive and transmit buffers to reduce cpu intervention. a maximum of two scbs (scb0, scb1) are available. i 2 c mode: the i 2 c peripheral is compatible with the i 2 c standard-mode, fast-mode, and fast-mode-plus devices as defined in the nxp i 2 c-bus specification and user manual (um10204). the i 2 c bus i/o is implemented with gpios in open-drain modes. the hardware i 2 c block implements a full multimaster and slave interface (it is capable of multimaster arbitration). this block is capable of operating at speeds of up to 1 mbps (fast-mode plus) and has flexible buffering options to reduce the interrupt overhead and latency for the cpu. the i 2 c function is imple- mented using the cypress-provided software component (ezi2c) that creates a mailbox address range in the memory of proc ble and effectively reduces the i 2 c communication to reading from and writing to an array in memory. in addition, the block supports an 8-byte fifo for receive and transmit, which, by increasing the time given for the cpu to read data, greatly reduces the need for clock stretching caused by the cpu not having read the data on time. when scb0 is used, serial data (sda) and serial clock (scl) of i 2 c can be connected to p0.4 and p0.5, or p1.4 and p1.5, or p3.0 and p3.1. when scb1 is used, sda and scl can be connected to p0.0 and p0.1, or p3.4 and p3.5, or p5.0 and p5.1. configurations for i 2 c are as follows: scb1 is fully compliant with the standard-mode (100 khz), fast-mode (400 khz), and fa st-mode-plus (1 mhz) i 2 c signaling specifications when r outed to gpio pins p5.0 and p5.1, except for hot-swap capability during i 2 c active commu- nication. scb1 is compliant only with standard mode (100 khz) when not used with p5.0 and p5.1. scb0 is compliant with standard mode (100 khz) only. uart mode: this is a full-feature uart operating up to 1 mbps. it supports automotive single-wire interface (lin), infrared interface (irda), and smartcard (iso7816) protocols. in addition, it supports the 9-bit multiprocessor mode, which allows addressing of peripherals connected over common rx and tx lines. the uart hardware flow control is supported to allow slow and fast devices to communicate with each other over uart without the risk of losing data. refer to ta b l e 4 on page 11 for possible uart connections to the gpios. spi mode: the spi mode supports full motorola? spi, texas instruments? secure simple pa iring (ssp) (essentially adds a start pulse used to synchronize spi codecs), and national microwire (half-duplex form of spi). the spi function is imple- mented using the cypress-provided software component (ezspi), which reduces the data interchange by reading and writing an array of memory. refer to table 4 on page 11 for the possible spi connections to the gpios. inter-ic sound bus (i 2 s) inter-ic sound bus (i 2 s) is a serial bus interface standard used for connecting digital audio device s. the specification is from philips ? semiconductor (i 2 s bus specification; february 1986, revised june 5, 1996). i 2 s operates only in the master mode, supporting the transmitter (tx) and the receiver (rx), which have independent data byte streams. these byte streams ar e packed with the most signif- icant byte first. the number of bytes used for each sample (a sample for the left or right channel) is the minimum number of bytes to hold a sample. lcd the lcd controller can drive up to four commons and up to 32 segments. it uses full digital me thods to drive the lcd segments providing ultra-low power consumption. the two methods used are referred to as digital correlation and pwm. the digital correlation method modulates the frequency and signal levels of the commons and segments to generate the highest rms voltage across a segment to light it up or to maintain the rms signal as zero. this method is good for stn displays but may result in reduced contrast in tn (cheaper) displays. the pwm method drives the panel with pwm signals to effec- tively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired lcd voltage. this method results in higher power consumption but provides better results in driving tn displays. lcd operation is supported during deep-sleep mode by refreshing a small display buffer (four bits; one 32-bit register per port).
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 7 of 42 capsense capsense is supported on all gpios through a capacitive sigma-delta (csd) block, which can be connected to any gpio through an analog mux bus. any gpio pin can be connected to the analog mux bus via an analog switch. the capsense function can thus be provided on any pin or group of pins in a system under software control. a software component in psoc creator is provided for the capsense block to make it easy for the user. the shield voltage can be driven on another mux bus to provide liquid-tolerance capabi lity. driving the shield electrode in phase with the sense electrode keeps the shield capacitance from attenuating the sensed input. the capsense trackpad/touchpad with gestures has the following features: supports 1-finger and 2-finger touch applications supports up to 35 x/y sensor inputs includes a gesture-detection library: ? 1-finger touch: tracing, pan, click, double-click ? 2-finger touch: pan, click, zoom i/o subsystem the i/o subsystem, which compri ses the gpio block, imple- ments the following: eight drive-strength modes: ? analog input mode (input and output buffers disabled) ? input only ? weak pull-up with strong pull-down ? weak pull-up with weak pull-down ? strong pull-up with weak pull-down ? strong pull-up with strong pull-down ? open drain with strong pull-down ? open drain with strong pull-up port pins: 36 input threshold select (cmos or lvttl) individual control of input and output buffers (enabling/disabling) in addition to drive-strength modes hold mode for latching the previous state (used for retaining the i/o state in deep sleep and hibernate modes) selectable slew rates for dv/dt to improve emi the gpio pins p5.0 and p5.1 are overvoltage-tolerant the gpio cells, including p5.0 and p5.1, cannot be hot-swapped or powered up indep endent of the rest of the system.
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 8 of 42 pinouts ta b l e 1 shows the pin list for the cybl10x6x device. table 1. cybl10x6x pin list (qfn package) pin name type description 1 vddd power 1.71-v to 5.5-v digital supply 2 xtal32o/p6.0 clock 32.768-khz crystal 3 xtal32i/p6.1 clock 32.768-khz crystal or external clock input 4 xres reset reset, active low 5 p4.0 gpio port 4 pin 0, analog/digital/lcd/csd 6 p4.1 gpio port 4 pin 1, analog/digital/lcd/csd 7 p5.0 gpio port 5 pin 0, analog/digital/lcd/csd 8 p5.1 gpio port 5 pin 1, analog/digital/lcd/csd 9 vssd ground digital ground 10 vddr power 1.9-v to 5.5-v radio supply 11 gant1 ground antenna shielding ground 12 ant antenna antenna pin 13 gant2 ground antenna shielding ground 14 vddr power 1.9-v to 5.5-v radio supply 15 vddr power 1.9-v to 5.5-v radio supply 16 xtal24i clock 24-mhz crystal or external clock input 17 xtal24o clock 24-mhz crystal 18 vddr power 1.9-v to 5.5-v radio supply 19 p0.0 gpio port 0 pin 0, analog/digital/lcd/csd 20 p0.1 gpio port 0 pin 1, analog/digital/lcd/csd 21 p0.2 gpio port 0 pin 2, analog/digital/lcd/csd 22 p0.3 gpio port 0 pin 3, analog/digital/lcd/csd 23 vddd power 1.71-v to 5.5-v digital supply 24 p0.4 gpio port 0 pin 4, analog/digital/lcd/csd 25 p0.5 gpio port 0 pin 5, analog/digital/lcd/csd 26 p0.6 gpio port 0 pin 6, analog/digital/lcd/csd 27 p0.7 gpio port 0 pin 7, analog/digital/lcd/csd 28 p1.0 gpio port 1 pin 0, analog/digital/lcd/csd 29 p1.1 gpio port 1 pin 1, analog/digital/lcd/csd 30 p1.2 gpio port 1 pin 2, analog/digital/lcd/csd 31 p1.3 gpio port 1 pin 3, analog/digital/lcd/csd 32 p1.4 gpio port 1 pin 4, analog/digital/lcd/csd 33 p1.5 gpio port 1 pin 5, analog/digital/lcd/csd 34 p1.6 gpio port 1 pin 6, analog/digital/lcd/csd 35 p1.7 gpio port 1 pin 7, analog/digital/lcd/csd 36 vdda power 1.71-v to 5.5-v analog supply 37 p2.0 gpio port 2 pin 0, analog/digital/lcd/csd 38 p2.1 gpio port 2 pin 1, analog/digital/lcd/csd 39 p2.2 gpio port 2 pin 2, analog/digital/lcd/csd 40 p2.3 gpio port 2 pin 3, analog/digital/lcd/csd
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 9 of 42 ta b l e 2 shows the pin list for the cybl10x6x device (wlcsp package). 41 p2.4 gpio port 2 pin 4, analog/digital/lcd/csd 42 p2.5 gpio port 2 pin 5, analog/digital/lcd/csd 43 p2.6 gpio port 2 pin 6, analog/digital/lcd/csd 44 p2.7 gpio port 2 pin 7, analog/digital/lcd/csd 45 vref ref 1.024-v reference 46 vdda power 1.71-v to 5.5-v analog supply 47 p3.0 gpio port 3 pin 0, analog/digital/lcd/csd 48 p3.1 gpio port 3 pin 1, analog/digital/lcd/csd 49 p3.2 gpio port 3 pin 2, analog/digital/lcd/csd 50 p3.3 gpio port 3 pin 3, analog/digital/lcd/csd 51 p3.4 gpio port 3 pin 4, analog/digital/lcd/csd 52 p3.5 gpio port 3 pin 5, analog/digital/lcd/csd 53 p3.6 gpio port 3 pin 6, analog/digital/lcd/csd 54 p3.7 gpio port 3 pin 7, analog/digital/lcd/csd 55 vssa ground analog ground 56 vccd power regulated 1.8-v supply; connect to 1-f capacitor 57 epad ground ground paddle for the qfn package table 1. cybl10x6x pin list (qfn package) (continued) pin name type description table 2. cybl10x6x pin list (wlcsp package) pin name type description a1 vref ref 1.024-v reference a2 vssa ground analog ground a3 p3.3 gpio port 3 pin 3, analog/digital/lcd/csd a4 p3.7 gpio port 3 pin 7, analog/digital/lcd/csd a5 vssd ground digital ground a6 vssa ground analog ground a7 vccd power regulated 1.8 v supply, connect to 1- f capacitor a8 vddd power 1.71-v to 5.5-v digital supply b1 p2.3 gpio port 2 pin 3, analog/digital/lcd/csd b2 vssa ground analog ground b3 p2.7 gpio port 2 pin 7, analog/digital/lcd/csd b4 p3.4 gpio port 3 pin 4, analog/digital/lcd/csd b5 p3.5 gpio port 3 pin 5, analog/digital/lcd/csd b6 p3.6 gpio port 3 pin 6, analog/digital/lcd/csd b7 xtal32i/p6.1 clock 32.768-khz crystal or external clock input b8 xtal32o/p6.0 clock 32.768-khz crystal c1 vssa ground analog ground c2 p2.2 gpio port 2 pin 2, analog/digital/lcd/csd c3 p2.6 gpio port 2 pin 6, analog/digital/lcd/csd c4 p3.0 gpio port 3 pin 0, analog/digital/lcd/csd
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 10 of 42 c5 p3.1 gpio port 3 pin 1, analog/digital/lcd/csd c6 p3.2 gpio port 3 pin 2, analog/digital/lcd/csd c7 xres reset reset, active low c8 p4.0 gpio port 4 pin 0, analog/digital/lcd/csd d1 p1.7 gpio port 1 pin 7, analog/digital/lcd/csd d2 vdda power 1.71-v to 5.5-v analog supply d3 p2.0 gpio port 2 pin 0, analog/digital/lcd/csd d4 p2.1 gpio port 2 pin 1, analog/digital/lcd/csd d5 p2.5 gpio port 2 pin 5, analog/digital/lcd/csd d6 vssd ground digital ground d7 p4.1 gpio port 4 pin 1, analog/digital/lcd/csd d8 p5.0 gpio port 5 pin 0, analog/digital/lcd/csd e1 p1.2 gpio port 1 pin 2, analog/digital/lcd/csd e2 p1.3 gpio port 1 pin 3, analog/digital/lcd/csd e3 p1.4 gpio port 1 pin 4, analog/digital/lcd/csd e4 p1.5 gpio port 1 pin 5, analog/digital/lcd/csd e5 p1.6 gpio port 1 pin 6, analog/digital/lcd/csd e6 p2.4 gpio port 2 pin 4, analog/digital/lcd/csd e7 p5.1 gpio port 5 pin 1, analog/digital/lcd/csd e8 vssd ground digital ground f1 vssd ground digital ground f2 p0.7 gpio port 0 pin 7, analog/digital/lcd/csd f3 p0.3 gpio port 0 pin 3, analog/digital/lcd/csd f4 p1.0 gpio port 1 pin 0, analog/digital/lcd/csd f5 p1.1 gpio port 1 pin 1, analog/digital/lcd/csd f6 vssr ground radio ground f7 vssr ground radio ground f8 vddr power 1.9-v to 5.5-v radio supply g1 p0.6 gpio port 0 pin 6, analog/digital/lcd/csd g2 vddd power 1.71-v to 5.5-v digital supply g3 p0.2 gpio port 0 pin 2, analog/digital/lcd/csd g4 vssd ground digital ground g5 vssr ground radio ground g6 vssr ground radio ground g7 gant ground antenna shielding ground g8 vssr ground radio ground h1 p0.5 gpio port 0 pin 5, analog/digital/lcd/csd h2 p0.1 gpio port 0 pin 1, analog/digital/lcd/csd h3 xtal24o clock 24-mhz crystal h4 xtal24i clock 24-mhz crystal or external clock input table 2. cybl10x6x pin list (wlcsp package) (continued) pin name type description
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 11 of 42 the i/o subsystem consists of a high-speed i/ o matrix (hsiom), which is a group of high -speed switches that routes gpios to the resources inside the devi ce. these resources incl ude capsense, tcpwms, i 2 c, spi, uart, and lcd. hsiom_port_selx are 32-bit-wide registers that contro l the routing of gpios. each register controls on e port; four dedicated bits are assigned to e ach gpio in the port. this provides up to 16 different options for gpio routing as shown in table 3 . the selection of peripheral functions for different gpio pins is given in table 4 . h5 vssr ground radio ground h6 vssr ground radio ground h7 ant antenna antenna pin j1 p0.4 gpio port 0 pin 4, analog/digital/lcd/csd j2 p0.0 gpio port 0 pin 0, analog/digital/lcd/csd j3 vddr power 1.9-v to 5.5-v radio supply j6 vddr power 1.9-v to 5.5-v radio supply j7 no connect - table 3. hsiom port settings value description 0 firmware-controlled gpio 1 reserved 2 reserved 3 reserved 4 pin is a csd sense pin 5 pin is a csd shield pin 6 pin is connected to amuxa 7 pin is connected to amuxb 8 pin-specific active function #0 9 pin-specific active function #1 10 pin-specific active function #2 11 reserved 12 pin is an lcd common pin 13 pin is an lcd segment pin 14 pin-specific deep-sleep function #0 15 pin-specific deep-sleep function #1 table 4. port pin connections name analog digital (hsiom_port_selx.sely) ('x' denote s port number and 'y' denotes pin number) 0 8 9 10 14 15 gpio active #0 active #1 active #2 deep sleep #0 deep sleep #1 p0.0 gpio tcpwm0_p[3] scb1_uart_rx[1] scb1_i2c_sda[1] scb1_spi_mosi[1] p0.1 gpio tcpwm0_n[3] scb1_uart_tx[1] scb1_i2c_scl[1] scb1_spi_miso[1] p0.3 gpio tcpwm1_n[3] scb1_uart_cts[1] scb1_spi_sclk[1] p0.4 gpio tcpwm1_p[0] scb0_uart_rx[1] ext_clk[0]/ eco_out[0] scb0_i2c_sda[1] scb0_spi_mosi[1] p0.5 gpio tcpwm1_n[0] scb0_uart_tx[1] scb0_i2c_scl[1] scb0_spi_miso[1] table 2. cybl10x6x pin list (wlcsp package) (continued) pin name type description
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 12 of 42 p0.6 gpio tcpwm2_p[0] scb0_uart_rts[1] swdio[0] scb0_spi_ss0[1] p0.7 gpio tcpwm2_n[0] scb0_uart_c ts[1] swdclk[0] scb0_spi_sclk[1] p1.0 gpio tcpwm0_p[1] wco_out[2] p1.1 gpio tcpwm0_n[1] scb1_spi_ss1 p1.2 gpio tcpwm1_p[1] scb1_spi_ss2 p1.3 gpio tcpwm1_n[1] scb1_spi_ss3 p1.4 gpio tcpwm2_p[1] scb0_uart_rx[0] scb0_i2c_sda[0] scb0_spi_mosi[1] p1.5 gpio tcpwm2_n[1] scb0_uart_tx[0] scb0_i2c_scl[0] scb0_spi_miso[1] p1.6 gpio tcpwm3_p[1] scb0_uart_rts[0] scb0_spi_ss0[1] p1.7 gpio tcpwm3_n[1] scb0_uart_cts[0] scb0_spi_sclk[1] p2.0 gpio scb0_spi_ss1 p2.1 gpio scb0_spi_ss2 p2.2 gpio wakeup scb0_spi_ss3 p2.3 gpio wco_out[1] p2.4 gpio p2.5 gpio p2.6 gpio p2.7 gpio ext_clk[1]/ eco_out[1] p3.0 sarmux_0 gpio tcpwm0_p[2] scb0_uart_rx[2] scb0_i2c_sda[2] p3.1 sarmux_1 gpio tcpwm0_n[2] scb0_uart_tx[2] scb0_i2c_scl[2] p3.2 sarmux_2 gpio tcpwm1_p[2] scb0_uart_rts[2] p3.3 sarmux_3 gpio tcpwm1_n[2] scb0_uart_cts[2] p3.4 sarmux_4 gpio tcpwm2_p[2] scb1_uart_rx[2] scb1_i2c_sda[2] p3.5 sarmux_5 gpio tcpwm2_n[2] scb1_uart_tx[2] scb1_i2c_scl[2] p3.6 sarmux_6 gpio tcpwm3_p[2] scb1_uart_rts[2] p3.7 sarmux_7 gpio tcpwm3_n[2] scb1_uart_cts[2] wco_out[0] p4.0 cmod gpio tcpwm0_p[0] scb1_uart_rts[0] scb1_spi_mosi[0] p4.1 ctank gpio tcpwm0_n[0] scb1_uart_cts[0] scb1_spi_miso[0] p5.0 gpio tcpwm3_p[0] scb1_uart_rx[0] extpa_en scb1_i2c_sda[0] scb1_spi_ss0[0] p5.1 gpio tcpwm3_n[0] scb1_uart_tx[0] ext_clk[2]/ eco_out[2] scb1_i2c_scl[0] scb1_spi_sclk[0] p6.0_xtal32o gpio p6.1_xtal32i gpio table 4. port pin connections (continued) name analog digital (hsiom_port_selx.sely) ('x' denote s port number and 'y' denotes pin number) 0 8 9 10 14 15 gpio active #0 active #1 active #2 deep sleep #0 deep sleep #1
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 13 of 42 power proc ble can be supplied from batteries with a voltage range of 1.9 v to 5.5 v by directly connecting to the digital supply (v ddd ), analog supply (v dda ), and radio supply (v ddr ) pins. the internal ldos in the device regulate the supply voltage to required levels for different blocks. the device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. the analog circuits run directly from the analog supply (v dda ) input. the device uses separate regulators for deep sleep and hibernate modes to minimize the power consumption. the radio stops wo rking below 1.9 v, but the rest of the system continues to function down to 1.71 v without rf. bypass capacitors must be used fr om vddx (x = a, d, or r) to ground. the typical practice for systems in this frequency range is to use a capacitor in the 1-f range in parallel with a smaller capacitor (for example, 0.1 f). note that these are simply rules of thumb and that, for critical ap plications, the pcb layout, lead inductance, and the bypass capacitor parasitic should be simulated to design to obtain optimal bypassing. low-power modes proc ble supports five power modes. refer to ta b l e 5 for more details on the system status. the proc ble device consumes the lowest current in stop mo de; the device wakeup from stop mode is with a system reset through the xres or wakeup pin. it can retain the sram data in hibernate mode and is capable of retaining the complete system status in deep-sleep mode. ta b l e 5 shows the different power modes and the peripherals that are active. power supply bypass capacitors v ddd 0.1-f ceramic at each pin plus bulk capacitor 1 f to 10 f v dda 0.1-f ceramic at each pin plus bulk capacitor 1 f to 10 f v ddr 0.1-f ceramic at each pin plus bulk capacitor 1 f to 10 f v ccd 1-f ceramic capacitor at the vccd pin v ref (optional) the internal bandgap may be bypassed with a 1-f to 10-f capacitor note 1. for cpu subsystem. table 5. power modes system status power mod e current consumption code execution digital peripherals available analog peripherals available clock sources available wake up sources wake-up time active 850 a + 260 a per mhz [1] yes all all all ? ? sleep 1.1 ma at 3 mhz no all all all any interrupt source 0 deep sleep 1.3 a no wdt, lcd, i 2 c/spi, link-layer por, bod wco, ilo gpio, wdt, i 2 c/spi link layer 25 s hibernate 150 na no no por, bod no gpio 2 ms stop 60 na no no no no wake-up pin, xres 2 ms
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 14 of 42 a typical system application connection diagram for the 56-qfn package is shown in figure 4 . figure 4. proc ble applications diagram
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 15 of 42 development support the cybl10x6x family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. visit www.cypress.com/procble to find out more. documentation a suite of documentation supports the cybl10x6x family to ensure that you find answers to your questions quickly. this section contains a list of some of the key documents. component datasheets: psoc creator components provide hardware abstraction using apis to configure and control peripheral activity. the component datasheet covers component features, its usage and operation details, api description, and electrical specif ications. this is the primary documentation used during development. these components can represent peripherals on the device (such as a timer, i 2 c, or uart) or high-level system functions (such as the ble component). application notes: application notes help you to understand how to use various device features. they also provide guidance on how to solve a variety of system design challenges. technical reference manual (trm): the trm describes all peripheral functionality in detail, with register-level descriptions. this document is divided into two parts: the architecture trm and the register trm. online in addition to the print documentation, cypress forums connect you with fellow users and experts from around the world, 24 hours a day, 7 days a week. tools with industry-standard cores, programming, and debugging interfaces, the cybl10x6x family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest infor- mation on the revolutionary, easy-to-use psoc creator ide, supported third-party compilers, programmers, and debuggers. kits cypress provides a portfolio of kits to accelerate time-to-market. visit us at www.cypress.com/procble .
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 16 of 42 electrical specifications this section provides detailed electrical characteristics. absolute maximum rating for the cybl10x6x devices is listed in the following table. usage above the absolute maximum conditions may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods of time may affect device reliability. the maximum storage temperature is 150 c in compliance with jedec standard jesd22-a103, high temperature storage life. when used below absolute maximum conditions, but above normal operating conditions, the device may not operate to the specification. absolute maximum ratings ble subsystem note 2. this does not apply to the rf pins (ant, xtali, and xtalo) . rf pins (ant, xtali, and xtalo) are tested for 500-v hbm. table 6. absolute maximum ratings spec id# parameter description min typ max units details/ conditions sid1 v ddd_abs analog, digital, or radio supply relative to v ss (v ssd = v ssa ) ?0.5 ? 6 v absolute max sid2 v ccd_abs direct digital core voltage input relative to v ssd ?0.5 ? 1.95 v absolute max sid3 v gpio_abs gpio voltage ?0.5 ? v dd +0.5 v absolute max sid4 i gpio_abs maximum current per gpio ?25 ? 25 ma absolute max sid5 i gpio_injection gpio injection cu rrent, max for v ih > v ddd , and min for v il < v ss ?0.5 ? 0.5 ma absolute max, current injected per pin bid57 esd_hbm electrostatic discharge human body model 2200 [2] ?? v bid58 esd_cdm electrostatic discharge charged device model 500 ? ? v bid61 lu pin current for latch up ?200 ? 200 ma table 7. ble subsystem spec id# parameter description min typ max units details/ conditions rf receiver specifications sid340 rxs, idle rx sensitivity with idle transmitter ? ?90 ? dbm sid340a rxs, idle rx sensitivity with idle transmitter excluding balun loss ? ?92 ? dbm guaranteed by design simulation sid341 rxs, dirty rx sensitivity with dirty transmitter ? ?87 ?70 dbm rf-phy specification (rcv-le/ca/01/c) sid342 rxs, highgain rx sensitivity in high-gain mode with idle transmitter ? ?92 ? dbm sid343 prxmax maximum input power ?10 ?1 ? dbm rf-phy specification (rcv-le/ca/06/c) sid344 ci1 co-channel interference, wanted signal at ?67 dbm and interferer at f rx ? 9 21 db rf-phy specification (rcv-le/ca/03/c)
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 17 of 42 sid345 ci2 adjacent channel interference wanted signal at ?67 dbm and interferer at frx 1 mhz ? 3 15 db rf-phy specification (rcv-le/ca/03/c) sid346 ci3 adjacent channel interference wanted signal at ?67 dbm and interferer at f rx 2 mhz ? ?29 ? db rf-phy specification (rcv-le/ca/03/c) sid347 ci4 adjacent channel interference wanted signal at ?67 dbm and interferer at f rx 3 mhz ? ?39 ? db rf-phy specification (rcv-le/ca/03/c) sid348 ci5 adjacent channel interference wanted signal at ?67 dbm and interferer at image frequency (f image ) ? ?20 ? db rf-phy specification (rcv-le/ca/03/c) sid349 ci3 adjacent channel interference wanted signal at ?67 dbm and interferer at image frequency (f image 1 mhz) ? ?30 ? db rf-phy specification (rcv-le/ca/03/c) sid350 obb1 out-of-band blocking, wanted signal at ?67 dbm and interferer at f = 30?2000 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid351 obb2 out-of-band blocking, wanted signal at ?67 dbm and interferer at f = 2,003?2,399 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid352 obb3 out-of-band blocking, wanted signal at ?67 dbm and interferer at f = 2,484?2,997 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid353 obb4 out-of-band blocking, wanted signal a ?67 dbm and inter- ferer at f = 3,000?12,750 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid354 imd intermodulation performance wanted signal at ?64 dbm and 1-mbps ble, third, fourth, and fifth offset channel ?50 ? ? dbm rf-phy specification (rcv-le/ca/05/c) sid355 rxse1 receiver spurious emission 30 mhz to 1.0 ghz ? ? ?57 dbm 100-khz measurement bandwidth etsi en300 328 v1.8.1 sid356 rxse2 receiver spurious emission 1.0 ghz to 12.75 ghz ? ? ?47 dbm 1-mhz measurement bandwidth etsi en300 328 v1.8.1 rf transmitter specifications sid357 txp, acc rf power accuracy ? ? 4 db sid358 txp, range rf power control range ? 20 ? db sid359 txp, 0 dbm output power, 0-db gain setting (pa7) ?4 0 3 dbm table 7. ble subsystem (continued) spec id# parameter description min typ max units details/ conditions
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 18 of 42 sid360 txp, max output power, maximum power setting (pa10) ?1 3 6 dbm sid361 txp, min output power, minimum power setting (pa1) ? ?18 ? dbm sid362 f2avg average frequency deviation for 10101010 pattern 185 ? ? khz rf-phy specification (trm-le/ca/05/c) sid363 f1avg average frequency deviation for 11110000 pattern 225 250 275 khz rf-phy specification (trm-le/ca/05/c) sid364 eo eye opening = ? f2avg/ ? f1avg 0.8 ? ? rf-phy specification (trm-le/ca/05/c) sid365 ftx, acc frequency accuracy ?150 ? 150 khz rf-phy specification (trm-le/ca/06/c) sid366 ftx, maxdr maximum frequency dr ift ?50 ? 50 khz rf-phy specification (trm-le/ca/06/c) sid367 ftx, initdr initial frequency dr ift ?20 ? 20 khz rf-phy specification (trm-le/ca/06/c) sid368 ftx,dr maximum drift rate ?20 ? 20 khz/ 50 s rf-phy specification (trm-le/ca/06/c) sid369 ibse1 in-band spurious emission at 2-mhz offset ? ? ?20 dbm rf-phy specification (trm-le/ca/03/c) sid370 ibse2 in-band spurious emission at 3-mhz offset ? ? ?30 dbm rf-phy specification (trm-le/ca/03/c) sid371 txse1 transmitter spurious emissions (average), <1.0 ghz ? ? ?55.5 dbm fcc-15.247 sid372 txse2 transmitter spurious emissions (average), >1.0 ghz ? ? ?41.5 dbm fcc-15.247 rf current specification sid373 irx receive current in normal mode ? 18.7 ? ma sid373a irx_rf receive current in normal mode ? 16.4 ? ma measured at v ddr sid374 irx, highgain receive current in high-gain mode ? 21.5 ? ma sid375 itx, 3 dbm tx current at 3-dbm setting (pa10) ? 20 ? ma sid376 itx, 0 dbm tx current at 0-dbm setting (pa7) ? 16.5 ? ma sid376a itx_rf, 0 dbm tx current at 0-dbm setting (pa7) ? 15.6 ? ma measured at v ddr sid376b itx_rf, 0 dbm tx current at 0 dbm excluding balun loss ? 14.2 ? ma guaranteed by design simulation sid377 itx, -3 dbm tx current at ?3-dbm setting (pa4) ? 15.5 ? ma sid378 itx, -6 dbm tx current at ?6-dbm setting (pa3) ? 14.5 ? ma sid379 itx, -12 dbm tx current at ?12-dbm setting (pa2) ? 13.2 ? ma sid380 itx, -18 dbm tx current at ?18-dbm setting (pa1) ? 12.5 ? ma sid380a iavg_1sec, 0dbm average current at 1-second ble connection interval ? 18.9 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy table 7. ble subsystem (continued) spec id# parameter description min typ max units details/ conditions
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 19 of 42 device-level specifications all specifications are valid for ?40 c ? ta ? 85 c and tj ? 100 c, except where no ted. specifications are valid for 1.71 v to 5.5 v, except where noted. sid380b iavg_4sec, 0dbm average current at 4-second ble connection interval ? 5.7 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy general rf specification sid381 freq rf operating frequency 2400 ? 2482 mhz sid382 chbw channel spacing ? 2 ? mhz sid383 dr on-air data rate ? 1000 ? kbps sid384 idle2tx ble radio idle to ble radio tx transition time ? 120 140 s sid385 idle2rx ble radio idle to ble radio rx transition time ?75120 s rssi specification sid386 rssi, acc rssi accuracy ? 5 ? db sid387 rssi, res rssi resolution ? 1 ? db sid388 rssi, per rssi sample period ? 6 ? s table 7. ble subsystem (continued) spec id# parameter description min typ max units details/ conditions table 8. dc specifications spec id# parameter description min typ max units details/ conditions sid6 v dd power supply input voltage (v dda = v ddd = v dd ) 1.8 ? 5.5 v with regulator enabled sid7 v dd power supply input voltage unregu- lated (v dda = v ddd = v dd ) 1.71 1.8 1.89 v internally unregulated supply sid8 v ddr radio supply voltage (radio on) 1.9 ? 5.5 v sid8a v ddr radio supply voltage (radio off) 1.71 ? 5.5 v sid9 v ccd digital regulator output voltage (for core logic) ?1.8? v sid10 c vccd digital regulator output bypass capacitor 11.31.6f x5r ceramic or better active mode, v dd = 1.71 v to 5.5 v sid13 i dd3 execute from flash; cpu at 3 mhz ? 1.7 ? ma t = 25 c, v dd = 3.3 v sid14 i dd4 execute from flash; cpu at 3 mhz ? ? ? ma t = ?40 c to 85 c sid15 i dd5 execute from flash; cpu at 6 mhz ? 2.5 ? ma t = 25 c, v dd = 3.3 v sid16 i dd6 execute from flash; cpu at 6 mhz ? ? ? ma t = ?40 c to 85 c sid17 i dd7 execute from flash; cpu at 12 mhz ? 4 ? ma t = 25 c, v dd = 3.3 v sid18 i dd8 execute from flash; cpu at 12 mhz ? ? ? ma t = ?40 c to 85 c sid19 i dd9 execute from flash; cpu at 24 mhz ? 7.1 ? ma t = 25 c, v dd = 3.3 v
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 20 of 42 sid20 i dd10 execute from flash; cpu at 24 mhz ? ? ? ma t = ?40 c to 85 c sid21 i dd11 execute from flash; cpu at 48 mhz ? 13.4 ? ma t = 25 c, v dd = 3.3 v sid22 i dd12 execute from flash; cpu at 48 mhz ? ? ? ma t = ?40 c to 85 c sleep mode, v dd = 1.8 to 5.5 v sid23 i dd13 imo on ? ? ? ma t = 25 c, v dd = 3.3 v, sysclk = 3 mhz sleep mode, v dd and v ddr = 1.9 to 5.5 v sid24 i dd14 eco on ? ? ? ma t = 25 c, v dd = 3.3 v, sysclk = 3 mhz deep-sleep mode, v dd = 1.8 to 3.6 v sid25 i dd15 wdt with wco on ? 1.3 ? a t = 25 c, v dd = 3.3 v sid26 i dd16 wdt with wco on ? ? ? a t = ?40 c to 85 c deep-sleep mode, v dd = 3.6 to 5.5 v sid27 i dd17 wdt with wco on ? ? ? a t = 25 c, v dd = 5 v sid28 i dd18 wdt with wco on ? ? ? a t = ?40 c to 85 c deep-sleep mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid29 i dd19 wdt with wco on ? ? ? a t = 25 c sid30 i dd20 wdt with wco on ? ? ? a t = ?40 c to 85 c hibernate mode, v dd = 1.8 to 3.6 v sid37 i dd27 gpio and reset active ? 150 ? na t = 25 c, v dd = 3.3 v sid38 i dd28 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 3.6 to 5.5 v sid39 i dd29 gpio and reset active ? ? ? na t = 25 c, v dd = 5 v sid40 i dd30 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid41 i dd31 gpio and reset active ? ? ? na t = 25 c sid42 i dd32 gpio and reset active ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.8 to 3.6 v sid43 i dd33 stop-mode current (v dd ) ? 20 ? na t = 25 c, v dd = 3.3 v sid44 i dd34 stop-mode current (v ddr ) ? 40 ?- na t = 25 c, v ddr = 3.3 v sid45 i dd35 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c sid46 i dd36 stop-mode current (v ddr ) ? ? ? na t = ?40 c to 85 c, v ddr = 1.9 v to 3.6 v stop mode, v dd = 3.6 to 5.5 v sid47 i dd37 stop-mode current (v dd ) ???nat = 25 c, v dd = 5 v table 8. dc specifications (continued) spec id# parameter description min typ max units details/ conditions
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 21 of 42 gpio sid48 i dd38 stop-mode current (v ddr ) ???nat = 25 c, v ddr = 5 v sid49 i dd39 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c sid50 i dd40 stop-mode current (v ddr ) ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid51 i dd41 stop-mode current (v dd ) ???nat = 25 c sid52 i dd42 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c table 8. dc specifications (continued) spec id# parameter description min typ max units details/ conditions table 9. ac specifications spec id# parameter description min typ max units details/ conditions sid53 f cpu cpu frequency dc ? 48 mhz 1.71 v ?? v dd ?? 5.5 v sid54 t sleep wakeup from sleep mode ? 0 ? s guaranteed by characterization sid55 t deepsleep wakeup from deep-sleep mode ? ? 25 s 24-mhz imo. guaranteed by characterization sid56 t hibernate wakeup from hibernate mode ? ? 2 ms guaranteed by characterization sid57 t stop wakeup from stop mode ? ? 2 ms guaranteed by characterization note 3. v ih must not exceed v dd + 0.2 v. table 10. gpio dc specifications spec id# parameter description min typ max units details/ conditions sid58 v ih input voltage high threshold 0.7 v dd ? ? v cmos input sid59 v il input voltage low threshold ? ? 0.3 v dd v cmos input sid60 v ih lvttl input, v dd < 2.7 v 0.7 v dd ? - v sid61 v il lvttl input, v dd < 2.7 v ? ? 0.3 v dd v sid62 v ih lvttl input, v dd >= 2.7 v 2.0 ? - v sid63 v il lvttl input, v dd >= 2.7 v ? ? 0.8 v sid64 v oh output voltage high level v dd ?0.6 ? ? v i oh = 4 ma at 3.3-v v dd sid65 v oh output voltage high level v dd ?0.5 ? ? v i oh = 1 ma at 1.8-v v dd sid66 v ol output voltage low level ? ? 0.6 v i ol = 8 ma at 3.3-v v dd sid67 v ol output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8-v v dd sid68 v ol output voltage low level ? ? 0.4 v i ol = 3 ma at 3.3-v v dd sid69 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid70 r pulldown pull-down resistor 3.5 5.6 8.5 k ?
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 22 of 42 table 12. ovt gpio dc specif ications (p5_0 and p5_1 only) sid71 i il input leakage current (absolute value) ? ? 2 na 25 c, v dd = 3.3 v sid72 i il_ctbm input leakage on ctbm input pins ? ? 4 na sid73 c in input capacitance ? ? 7 pf sid74 v hysttl input hysteresis lvttl 25 40 mv v dd > 2.7 v sid75 v hyscmos input hysteresis cmos 0.05 v dd ? ? mv sid76 i diode current through protection diode to v dd /v ss ? ? 100 a sid77 i tot_gpio maximum total source or sink chip current ? ? 200 ma table 10. gpio dc specifications (continued) spec id# parameter description min typ max units details/ conditions table 11. gpio ac specifications spec id# parameter description min typ max units details/ conditions sid78 t risef rise time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf sid79 t fallf fall time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf sid80 t rises rise time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf sid81 t falls fall time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf sid82 f gpiout1 gpio fout; 3.3 v ? v dd ?? 5.5 v. fast-strong mode ? ? 33 mhz 90/10%, 25 pf load, 60/40 duty cycle sid83 f gpiout2 gpio fout; 1.7 v ?? v dd ?? 3.3 v. fast-strong mode ? ? 16.7 mhz 90/10%, 25 pf load, 60/40 duty cycle sid84 f gpiout3 gpio fout; 3.3 v ?? v dd ?? 5.5 v. slow-strong mode ? ? 7 mhz 90/10%, 25 pf load, 60/40 duty cycle sid85 f gpiout4 gpio fout; 1.7 v ?? v dd ?? 3.3 v. slow-strong mode ? ? 3.5 mhz 90/10%, 25 pf load, 60/40 duty cycle sid86 f gpioin gpio input operating frequency. 1.71 v ?? v dd ?? 5.5 v ? ? 48 mhz 90/10% v io spec id# parameter description min typ max units details/ conditions sid71a i il input leakage (absolute value). v ih > v dd 10 a 25c, v dd = 0 v, v ih = 3.0 v sid66a v ol output voltage low level ? ? 0.4 v i ol = 20 ma, v dd > 2.9 v
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 23 of 42 table 13. ovt gpio ac specif ications (p5_0 and p5_1 only) xres spec id# parameter description min typ max units details/ conditions sid78a t rise_ovfs output rise time in fast-strong mode 1.5 ? 12 ns 25-pf load, 10%?90%, v dd =3.3 v sid79a t fall_ovfs output fall time in fast-strong mode 1.5 ? 12 ns 25-pf load, 10%?90%, v dd =3.3 v sid80a t risess output rise time in slow-strong mode 10 ? 60 ns 25 pf load, 10%-90%, v dd = 3.3 v sid81a t fallss output fall time in slow-strong mode 10 ? 60 ns 25 pf load, 10%-90%, v dd = 3.3 v sid82a f gpiout1 gpio f out ; 3.3 v ? v dd 5.5 v fast-strong mode ? ? 24 mhz 90/10%, 25 pf load, 60/40 duty cycle sid83a f gpiout2 gpio f out ; 1.71 v ? v dd 3.3 v fast-strong mode ? ? 16 mhz 90/10%, 25 pf load, 60/40 duty cycle table 14. xres dc specifications spec id# parameter description min typ max units details/ conditions sid87 v ih input voltage high threshold 0.7 v ddd ? ? v cmos input sid88 v il input voltage low threshold ? ? 0.3 v ddd v cmos input sid89 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid90 c in input capacitance ? 3 ? pf sid91 v hysxres input voltage hysteresis ? 100 ? mv sid92 i diode current through protection diode to v dd /v ss ??100a table 15. xres ac specifications spec id# parameter description min typ max units details/ conditions sid93 t resetwidth reset pulse width 1 ? ? s
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 24 of 42 analog peripherals temperature sensor sar adc table 16. temperature sensor specifications spec id# parameter description min typ max units details/conditions sid155 t sensacc temperature sensor accuracy ?5 1 5 c ?40 to +85 c table 17. sar adc dc specifications spec id# parameter description min typ max units details/conditions sid156 a_res resolution ? ? 12 bits sid157 a_chnis_s number of channels ? single-ended ? ? 8 8 full-speed sid158 a-chnks_d number of channels ? differential ? ? 4 differential inputs use neighboring i/o sid159 a-mono monotonicity ? ? ? yes sid160 a_gainerr gain error ? ? 0.1 % with external reference sid161 a_offset input offset voltage ? ? 2 mv measured with 1-v v ref sid162 a_isar current consumption ? ? 1 ma sid163 a_vins input voltage range ? single-ended v ss ?v dda v sid164 a_vind input voltage range ? differential v ss ? v dda v sid165 a_inres input resistance ? ? 2.2 k ? sid166 a_incap input capacitance ? ? 10 pf sid312 vrefsar trimmed internal reference to sar ?1 ? 1 % percentage of vbg (1.024 v) table 18. sar adc ac specifications spec id# parameter description min typ max units details/ conditions sid167 a_psrr power supply rejection ratio 70 ? ? db measured at 1 v sid168 a_cmrr common-mode rejection ratio 66 ? ? db sid169 a_samp sample rate ? ? 1 msps sid313 fsarintref sar operating speed without external reference bypass ? ? 100 ksps 12-bit resolution sid170 a_snr signal-to-noise ratio (snr) 65 ? ? db f in = 10 khz sid171 a_bw input bandwidth without aliasing ? ? a_samp/ 2 khz sid172 a_inl integral nonlinearity (inl). v dd = 1.71 to 5.5 v, 1 msps ?1.7 ? 2 lsb v ref = 1 v to v dd sid173 a_inl integral nonlinearity. v ddd = 1.71 to 3.6 v, 1 msps ?1.5 ? 1.7 lsb v ref = 1.71 v to v dd sid174 a_inl integral nonlinearity. v dd = 1.71 to 5.5 v, 500 ksps ?1.5 ? 1.7 lsb v ref = 1 v to v dd sid175 a_dnl differential nonlinearity (dnl). v dd = 1.71 to 5.5 v, 1 msps ?1 ? 2.2 lsb v ref = 1 v to v dd
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 25 of 42 csd sid176 a_dnl differential nonlinearity. v dd = 1.71 to 3.6 v, 1 msps ?1 ? 2 lsb v ref = 1.71 v to v dd sid177 a_dnl differential nonlinearity. v dd = 1.71 to 5.5 v, 500 ksps ?1 ? 2.2 lsb v ref = 1 v to v dd sid178 a_thd total harmonic distortion ? ? ?65 db f in = 10 khz table 18. sar adc ac specifications (continued) spec id# parameter description min typ max units details/ conditions table 19. csd block specifications spec id# parameter description min typ max units details/ conditions sid179 vcsd voltage range of operation 1.71 ? 5.5 v sid180 idac1 dnl for 8-bit resolution ?1 ? 1 lsb sid181 idac1 inl for 8-bit resolution ?3 ? 3 lsb sid182 idac2 dnl for 7-bit resolution ?1 ? 1 lsb sid183 idac2 inl for 7-bit resolution ?3 ? 3 lsb sid184 snr ratio of counts of finger to noise 5? ?ratio capacitance range of 9 pf to 35 pf; 0.1-pf sensitivity. radio is not operating during the scan sid185 idac1_crt1 output current of idac1 (8-bits) in high range ? 612 ? a sid186 idac1_crt2 output current of idac1 (8-bits) in low range ? 306 ? a sid187 idac2_crt1 output current of idac2 (7-bits) in high range ? 305 ? a sid188 idac2_crt2 output current of idac2 (7-bits) in low range ? 153 ? a
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 26 of 42 digital peripherals 4x tcpwm counter pulse width modulation (pwm) table 20. timer dc specifications spec id parameter description min typ max units details/conditions sid189 i tim1 block current consumption at 3 mhz ? ? 19 a 16-bit timer sid190 i tim2 block current consumption at 12 mhz ? ? 66 a 16-bit timer sid191 i tim3 block current consumption at 48 mhz ? ? 285 a 16-bit timer table 21. timer ac specifications spec id parameter description min typ max units details/conditions sid192 t timfreq operating frequency f clk ?48mhz sid193 t capwint capture pulse width (internal) 2 t clk ??ns sid194 t capwext capture pulse width (external) 2 t clk ??ns sid195 t timres timer resolution t clk ??ns sid196 t tenwidint enable pulse width (internal) 2 t clk ??ns sid197 t tenwidext enable pulse width (external) 2 t clk ??ns sid198 t timreswint reset pulse width (internal) 2 t clk ??ns sid199 t timresext reset pulse width (external) 2 t clk ??ns table 22. counter dc specifications spec id parameter description min typ max units details/conditions sid200 i ctr1 block current consumption at 3 mhz ? ? 19 a 16-bit counter sid201 i ctr2 block current consumption at 12 mhz ? ? 66 a 16-bit counter sid202 i ctr3 block current consumption at 48 mhz ? ? 285 a 16-bit counter table 23. counter ac specifications spec id parameter description min typ max units details/conditions sid203 t ctrfreq operating frequency f clk ?48mhz sid204 t ctrpwint capture pulse width (internal) 2 t clk ??ns sid205 t ctrpwext capture pulse width (external) 2 t clk ??ns sid206 t ctres counter resolution t clk ??ns sid207 t cenwidint enable pulse width (internal) 2 t clk ??ns sid208 t cenwidext enable pulse width (external) 2 t clk ??ns sid209 t ctrreswint reset pulse width (internal) 2 t clk ??ns sid210 t ctrreswext reset pulse width (external) 2 t clk ?? ns table 24. pwm dc specifications spec id parameter description min typ max units details/conditions sid211 i pwm1 block current consumption at 3 mhz ? ? 19 a 16-bit pwm sid212 i pwm2 block current consumption at 12 mhz ? ? 66 a 16-bit pwm sid213 i pwm3 block current consumption at 48 mhz ? ? 285 a 16-bit pwm
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 27 of 42 i 2 c lcd direct drive table 25. pwm ac specifications spec id parameter description min typ max units details/conditions sid214 t pwmfreq operating frequency f clk ?48mhz sid215 t pwmpwint pulse width (internal) 2 t clk ??ns sid216 t pwmext pulse width (external) 2 t clk ??ns sid217 t pwmkillint kill pulse width (internal) 2 t clk ??ns sid218 t pwmkillext kill pulse width (external) 2 t clk ??ns sid219 t pwmeint enable pulse width (internal) 2 t clk ??ns sid220 t pwmenext enable pulse width (external) 2 t clk ??ns sid221 t pwmreswint reset pulse width (internal) 2 t clk ??ns sid222 t pwmreswext reset pulse width (external) 2 t clk ??ns table 26. i 2 c dc specifications spec id parameter description min typ max units details/conditions sid223 i i2c1 block current consumption at 100 khz ? ? 10.5 a sid224 i i2c2 block current consumption at 400 khz ? ? 135 a sid225 i i2c3 block current consumption at 1 mbps ? ? 310 a sid226 i i2c4 i 2 c enabled in deep-sleep mode ? ? 1.4 a table 27. fixed i 2 c ac specifications spec id parameter description min typ max units details/conditions sid227 f i2c1 bit rate ? ? 1 mbps table 28. lcd direct drive dc specifications spec id parameter description min typ max units details/conditions sid228 i lcdlow operating current in low-power mode ? 5 ? a 16 4 small-segment display at 50 hz sid229 c lcdcap lcd capacitance per segment/common driver ? 500 5000 pf sid230 lcd offset long-term segment offset ? 20 ? mv sid231 i lcdop1 lcd system operating current. vbias = 5 v ? 2 ? ma 32 4 segments. 50 hz. 25 c sid232 i lcdop2 lcd system operating current. vbias = 3.3 v ? 2 ? ma 32 4 segments. 50 hz. 25 c table 29. lcd direct drive ac specifications spec id parameter description min typ max units details/conditions sid233 f lcd lcd frame rate 10 50 150 hz table 30. fixed uart dc specifications spec id parameter description min typ max units details/conditions sid234 i uart1 block current consumption at 100 kbps ? ? 9 a sid235 i uart2 block current consumption at 1000 kbps ? ? 312 a
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 28 of 42 spi specifications table 31. fixed uart ac specifications spec id parameter description min typ max units details/conditions sid236 f uart bit rate ? ? 1 mbps table 32. fixed spi dc specifications spec id parameter description min typ max units details/conditions sid237 i spi1 block current consumption at 1 mbps ? ? 360 a sid238 i spi2 block current consumption at 4 mbps ? ? 560 a sid239 i spi3 block current consumption at 8 mbps ? ? 600 a table 33. fixed spi ac specifications spec id parameter description min typ max units details/conditions sid240 f spi spi operating frequency (master; 6x oversampling) ?? 8mhz table 34. fixed spi master mode ac specifications spec id parameter description min typ max units details/conditions sid241 t dmo mosi valid after sclk driving edge ? ? 18 ns sid242 t dsi miso valid before sclk capturing edge. full clock, late miso sampling used 20 ? ? ns full clock, late miso sampling sid243 t hmo previous mosi data hold time 0 ? ? ns referred to slave capturing edge table 35. fixed spi slave mode ac specifications spec id parameter description min typ max units sid244 t dmi mosi valid before sclk capturing edge 40 ? ? ns sid245 t dso miso valid after sclk driving edge ? ? 42 + 3 t cpu ns sid246 t dso_ext miso valid after sclk driving edge in external clock mode. v dd < 3.0 v ? ? 50 ns sid247 t hso previous miso data hold time 0 ? ? ns sid248 t sselsck ssel valid to first sck valid edge 100 ? ? ns
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 29 of 42 memory system resources power-on-reset (por) table 36. flash dc specifications spec id parameter description min typ max units details/conditions sid249 v pe erase and program voltage 1.71 ? 5.5 v sid309 t ws48 number of wait states at 32?48 mhz 2 ? ? cpu execution from flash sid310 t ws32 number of wait states at 16?32 mhz 1 ? ? cpu execution from flash sid311 t ws16 number of wait states for 0?16 mhz 0 ? ? cpu execution from flash note 4. it can take as much as 20 ms to write to flash. during this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. reset sources include the xres pin, software resets , cpu lockup states and privilege violations, improper power supp ly levels, and watchdogs. make certain that these are not inadvertently activated. table 37. flash ac specifications spec id parameter description min typ max units details/conditions sid250 t rowwrite [4] row (block) write time (erase and program) ? ? 20 ms row (block) = 128 bytes sid251 t rowerase [4] row erase time ? ? 13 ms sid252 t rowprogram [4] row program time after erase ? ? 7 ms sid253 t bulkerase [4] bulk erase time (128 kb) ? ? 35 ms sid254 t devprog [4] total device program time ? ? 25 seconds sid255 f end flash endurance 100 k ? ? cycles sid256 f ret flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years sid257 f ret2 flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years table 38. por dc specifications spec id parameter description min typ max units details/conditions sid258 v riseipor rising trip voltage 0.80 ? 1.45 v sid259 v fallipor falling trip voltage 0.75 ? 1.40 v sid260 v iporhyst hysteresis 15 ? 200 mv table 39. por ac specifications spec id parameter description min typ max units details/conditions sid264 t ppor_tr precision power-on reset (ppor) response time in active and sleep modes ??1s
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 30 of 42 voltage monitors (lvd) table 40. brown-out detect spec id# parameter description min typ max units details/ conditions sid261 v fallppor bod trip voltage in active and sleep modes 1.64 ? ? v sid262 v falldpslp bod trip voltage in deep sleep 1.4 ? ? v table 41. hibernate reset spec id# parameter description min typ max units details/ conditions sid263 v hbrtrip bod trip voltage in hibernate 1.1 ? ? v table 42. voltage monitor dc specifications spec id parameter description min typ max units details/ conditions sid265 v lvi1 lvi_a/d_sel[3:0] = 0000b 1.71 1.75 1.79 v sid266 v lvi2 lvi_a/d_sel[3:0] = 0001b 1.76 1.80 1.85 v sid267 v lvi3 lvi_a/d_sel[3:0] = 0010b 1.85 1.90 1.95 v sid268 v lvi4 lvi_a/d_sel[3:0] = 0011b 1.95 2.00 2.05 v sid269 v lvi5 lvi_a/d_sel[3:0] = 0100b 2.05 2.10 2.15 v sid270 v lvi6 lvi_a/d_sel[3:0] = 0101b 2.15 2.20 2.26 v sid271 v lvi7 lvi_a/d_sel[3:0] = 0110b 2.24 2.30 2.36 v sid272 v lvi8 lvi_a/d_sel[3:0] = 0111b 2.34 2.40 2.46 v sid273 v lvi9 lvi_a/d_sel[3:0] = 1000b 2.44 2.50 2.56 v sid274 v lvi10 lvi_a/d_sel[3:0] = 1001b 2.54 2.60 2.67 v sid2705 v lvi11 lvi_a/d_sel[3:0] = 1010b 2.63 2.70 2.77 v sid276 v lvi12 lvi_a/d_sel[3:0] = 1011b 2.73 2.80 2.87 v sid277 v lvi13 lvi_a/d_sel[3:0] = 1100b 2.83 2.90 2.97 v sid278 v lvi14 lvi_a/d_sel[3:0] = 1101b 2.93 3.00 3.08 v sid279 v lvi15 lvi_a/d_sel[3:0] = 1110b 3.12 3.20 3.28 v sid280 v lvi16 lvi_a/d_sel[3:0] = 1111b 4.39 4.50 4.61 v sid281 lvi_idd block current ? ? 100 a table 43. voltage monitor ac specifications spec id parameter description min typ max units details/ conditions sid282 t montrip voltage monitor trip time ? ? 1 s
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 31 of 42 swd interface internal main oscillator internal low-speed oscillator table 44. swd interface specifications spec id parameter description min typ max units details/conditions sid283 f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk 1/3 cpu clock frequency sid284 f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk 1/3 cpu clock frequency sid285 t_swdi_setup t = 1/f swdclk 0.25 t ? ? ns sid286 t_swdi_hold t = 1/f swdclk 0.25 t ? ? ns sid287 t_swdo_valid t = 1/f swdclk ? ? 0.5 t ns sid288 t_swdo_hold t = 1/f swdclk 1 ? ? ns table 45. imo dc specifications spec id parameter description min typ max units details/conditions sid289 i imo1 imo operating current at 48 mhz ? ? 1000 a sid290 i imo2 imo operating current at 24 mhz ? ? 325 a sid291 i imo3 imo operating current at 12 mhz ? ? 225 a sid292 i imo4 imo operating current at 6 mhz ? ? 180 a sid293 i imo5 imo operating current at 3 mhz ? ? 150 a table 46. imo ac specifications spec id parameter description min typ max units details/conditions sid296 f imotol3 frequency variation from 3 to 48 mhz ? ? 2 % with api-called calibration sid297 f imotol3 imo startup time ? 12 ? s table 47. ilo dc specifications spec id parameter description min typ max units details/conditions sid298 i ilo2 ilo operating current at 32 khz ? 0.3 1.05 a table 48. ilo ac specifications spec id parameter description min typ max units details/conditions sid299 t startilo1 ilo startup time ? ? 2 ms sid300 f ilotrim1 32-khz trimmed frequency 15 32 50 khz table 49. external clock specifications spec id parameter description min typ max units details/conditions sid301 extclkfreq external clock input frequency 0 ? 48 mhz cmos input level only. ttl input is not supported sid302 extclkduty duty cycle; measured at v dd /2 45 ? 55 % cmos input level only. ttl input is not supported
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 32 of 42 table 50. eco specifications spec id# parameter description min typ max units details/ conditions sid389 f eco crystal frequency ? 24 ? mhz sid390 f tol frequency tolerance ?50 ? 50 ppm sid391 esr equivalent series resistance ? ? 60 ? sid392 pd drive level ? ? 100 w sid393 t start1 startup time (fast charge on) ? ? 850 s sid394 t start2 startup time (fast charge off) ? ? 3 ms sid395 c l load capacitance ? 8 ? pf sid396 c 0 shunt capacitance ? 1.1 ? pf sid397 i eco operating current ? 600 ? a table 51. wco specifications spec id# parameter description min typ max units details/ conditions sid398 f wco crystal frequency ? 32.768 ? khz sid399 f tol frequency tolerance ? 50 ? ppm sid400 esr equivalent se ries resistance ? 50 ? k ? sid401 pd drive level ? ? 1 w sid402 t start startup time ? ? 500 ms sid403 c l crystal load capacitance 6 ? 12.5 pf sid404 c 0 crystal shunt capacitance ? 1.35 ? pf sid405 i wco1 operating current (high-power mode) ?? 8a sid406 i wco2 operating current (low-power mode) ?? 1a
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 33 of 42 ordering information the cybl10x6x part numbers and features are listed in the following table. part numbering conventions the part numbers are of the form cybl10abc-de fghi where the fields are defined as follows. part number cpu speed (mhz) flash size (kb) capsense scb tcpwm 12-bit sar adc i 2 s pwm lcd package cybl10161-56lqxi 48 128 no 1 2 1 msps no no no 56-qfn cybl10162-56lqxi 48 128 no 2 4 1 msps no 4 no 56-qfn cybl10163-56lqxi 48 128 no 2 4 1 msps yes no no 56-qfn CYBL10461-56LQXI 48 128 yes 2 4 1 msps no no no 56-qfn cybl10462-56lqxi 48 128 yes 2 4 1 msps yes no no 56-qfn cybl10463-56lqxi 48 128 yes 2 4 1 msps no no yes 56-qfn cybl10561-56lqxi 48 128 yes (gestures) 2 4 1 msps no no no 56-qfn cybl10562-56lqxi 48 128 yes (gestures) 2 4 1 msps yes 1 no 56-qfn cybl10563-56lqxi 48 128 no 2 4 1 msps yes 1 yes 56-qfn cybl10563-68fnxi 48 128 no 2 4 1 msps yes 1 yes 68-wlcsp sub-family cypress prefix product type flash capacity package pins pb package code 10: cybl10xxx 6: 128 kb 56/68: number of pins lq: qfn fn: wlcsp example cybl 10 a e d c bfg h - 1: 4: 5: embedded only capsense touch cybl: proc-ble family x: with pb : pb-free i: industrial feature set i temperature range 3: part identifier
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 34 of 42 the field values are listed in the following table: field description values meaning cybl cypress proc ble family cybl 10 subfamily 10 cybl10x6x a product type 1 embedded only 4 capsense 5touch b flash capacity 6 128 kb c feature set de package pins 56 70 fg package code lq qfn fn wlcsp lt tape and reel h pb x pb-free x absent (with pb) i temperature range c commercial 0 c to 70 c i industrial ?40 c to 85 c
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 35 of 42 packaging table 52. package characteristics parameter description conditions min typ max units t a operating ambient temperature ?40 25 85 c t j operating junction temperature ?40 ? 100 c t ja package ? ja (56-pin qfn) ? 16.9 ? c/watt t jc package ? jc (56-pin qfn) ? 9.7 ? c/watt t ja package ? ja (68-ball wlcsp) ? 16.6 ? c/watt t jc package ? jc (68-ball wlcsp) ? 0.19 ? c/watt table 53. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 56-pin qfn 260 c 30 seconds 68-ball wlcsp 260 c 30 seconds table 54. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 56-pin qfn msl 3 68-ball wlcsp msl 1 table 55. package details spec id package description 001-58740 rev. *a 56-pin qfn 7 mm 7 mm 0.6 mm 001-92343 rev. ** 68-ball wlcsp 3.52 mm 3.91 mm 0.55 mm
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 36 of 42 figure 5. 56-pin qfn 7 mm 7 mm 0.6 mm the center pad on the qfn package must be connected to ground (vss) for the proper operation of the device. figure 6. 68-ball wlcsp package outline 001-58740 rev. *a h g f e d c b a 1 2 3 4 5 6 7 8 123 45678 h g f e d c b a top view bottom view side view j j notes: 1. reference jedec publication 95, design guide 4.18 2. all dimensions are in millimeters 001-92343 rev. **
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 37 of 42 acronyms table 56. acronyms used in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth can controller area network, a communications protocol cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dmips dhrystone million instructions per second dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fet field-effect transistor fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hci host controller interface hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol i 2 s inter-ic sound iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller table 56. acronyms used in this document (continued) acronym description
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 38 of 42 nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld pc program counter pcb printed circuit board pga programmable gain amplifier phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise power-on reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. soc start of conversion sof start of frame spi serial peripheral interface, a communications protocol sr slew rate table 56. acronyms used in this document (continued) acronym description sram static random access memory sres software reset stn super twisted nematic swd serial wire debug, a test protocol swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier tn twisted nematic trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 56. acronyms used in this document (continued) acronym description
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 39 of 42 document conventions units of measure table 57. units of measure symbol unit of measure c degrees celsius db decibel dbm decibel-milliwatts ff femtofarads hz hertz kb 1024 bytes kbps kilobits per second khr kilohour khz kilohertz k ? kilo ohm ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad h microhenry s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pf picofarad ppm parts per million ps picosecond ssecond sps samples per second sqrthz square root of hertz vvolt wwatt table 57. units of measure (continued) symbol unit of measure
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 40 of 42 errata this section describes the errata for proc ble. details includ e errata trigger conditions, scope of impact, and available worka round. contact your local cypress sales re presentative if you have questions. errata summary 1. power consumption in deep sleep mode problem definition power consumption measured during deep sleep mode will be 4.3 a against 1.3 a. parameters affected none trigger conditions this problem occurs only when using the blueto oth low energy (ble) component (version 1.0). scope of impact the current consumption is 3 a higher in deep sleep mode. workaround no workaround with ble component (version 1.0). fix status this problem will be fixed in the next release of the ble component. changes none 2. average current consumption at one-second and four-s econd ble connection intervals (sid380a and sid380b) problem definition average current consumption is higher for one-second and four-second ble connection intervals as follows: a) 26 ua versus target spec of 18.9 a at one -second connection interval at 0-dbm transmit power. b) 9.7 a versus target spec of 5.7 a at fou r-second connection interval at 0-dbm transmit power. parameters affected system current consumption will be higher trigger conditions this problem occurs only when using the ble component (version 1.0) firmware. scope of impact the current consumption is 7.1 a and 4 a higher for one-second and four-second ble connection intervals. workaround no workaround with ble component (version 1.0). fix status this problem will be fixed in the next release of the ble component firmware. no hardware parameters will change. changes none
preliminary proc ble: cybl10x6x family datasheet document number: 001-90478 rev. *f page 41 of 42 revision history description title: cybl10x6x family datasheet programmab le radio-on-chip with bluetooth low energy (proc ble) document number: 001-90478 revision ecn orig. of change submission date description of change *f 4567076 csai 11/11/2014 initial release
document number: 001-90478 rev. *f revised november 11, 2014 page 42 of 42 all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary proc ble: cybl10x6x family datasheet ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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